Block Diagram Of Address Match Detection Function - Fujitsu MB90480 Series Hardware Manual

21.2 Block Diagram of Address Match Detection Function

The address match detection module consists of the following blocks:
• Address latch
• Program address detection control status register (PACSR)
• Program address detection registers (RADR)
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Block Diagram of Address Match Detection Function
Figure 21.2-1 shows the block diagram of the address match detection function.
Reserved: Always set to "0"
❍ Address latch
The address latch stores the value of the address output to the internal data bus.
❍ Program address detection control status register (PACSR)
The program address detection control status register enables or disables output of an interrupt
at an address match.
❍ Program address detection registers (PADR0, PADR1)
The program address detection registers set the address that is compared with the value of the
address latch.
Note:
The addresses of the program address detection register are "1FF0
in the RAM area. Therefore, the access to the RAM area should not be performed during the use of
this function.
Figure 21.2-1 Block Diagram of the Address Match Detection Function
Address latch
PADR0 (24 bits)
Program address detection register 0
PADR1 (24 bits)
Program address detection register 1
PACSR
Reserved Reserved Reserved Reserved ADE1 Reserved ADE0
Program address detection control status register (PACSR)
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
INT9 instruction
(INT9 interrupt
generation)
Reserved
" to "1FF5 " and are included
H H
459