Table Of Contents - Fujitsu MB90480 Series Hardware Manual

CONTENTS
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES ........................................................ 1
1.1 Features of MB90480/485 Series .......................................................................................................... 2
1.2 Block Diagram of MB90480/485 Series ................................................................................................. 6
1.3 Package Dimensions ............................................................................................................................. 7
1.4 Pin Assignment ...................................................................................................................................... 9
1.5 Pin Functions ....................................................................................................................................... 11
1.6 I/O Circuit Type .................................................................................................................................... 18
1.7 Handling the Device ............................................................................................................................. 21
CHAPTER 2 CPU ............................................................................................................. 23
2.1 Overview of CPU Specifications .......................................................................................................... 24
2.2 Memory Space ..................................................................................................................................... 25
2.3 CPU Registers ..................................................................................................................................... 29
2.3.1 Accumulator (A) .............................................................................................................................. 31
2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 32
2.3.3 Processor Status (PS) .................................................................................................................... 33
2.3.4 Program Counter (PC) .................................................................................................................... 36
2.3.5 Program Counter Bank Register (PCB) .......................................................................................... 37
2.3.6 Direct Page Register (DPR) ........................................................................................................... 38
2.3.7 General-Purpose Register (Register Bank) .................................................................................... 39
2.4 Prefix Codes ........................................................................................................................................ 40
CHAPTER 3 INTERRUPT ................................................................................................ 43
3.1 Overview of Interrupt ........................................................................................................................... 44
3.2 Interrupt Factor and Interrupt Vector ................................................................................................... 46
3.3 Interrupt Control Register and Peripheral Function ............................................................................. 49
3.3.1 Interrupt Control Register (ICR00 to ICR15) .................................................................................. 50
3.4 Hardware Interrupt ............................................................................................................................... 53
3.4.1 Hardware Interrupt Operation ......................................................................................................... 56
3.4.2 Flow of Hardware Interrupt Operation ............................................................................................ 58
3.4.3 Procedure for Using Hardware Interrupt ......................................................................................... 59
3.4.4 Multiple Interrupts ........................................................................................................................... 61
3.4.5 Hardware Interrupt Processing Time .............................................................................................. 63
3.5 Software Interrupt ................................................................................................................................ 65
Interrupt by μDMAC ............................................................................................................................. 67
3.6
3.6.1 DMA Descriptor .............................................................................................................................. 70
3.6.2 Individual Registers of DMA Descriptor .......................................................................................... 72
μDMAC Processing Procedure ....................................................................................................... 75
3.6.3
μDMAC Processing Time ............................................................................................................... 76
3.6.4
3.7 Interrupt by Extended Intelligent I/O Service (EI
2
3.7.1 EI OS descriptor (ISD) ................................................................................................................... 80
3.7.2 Each Register of EI
3.7.3 Operation of EI
3.7.4 Procedure for Use of EI
2
OS Descriptor (ISD) ....................................................................................... 82
2
OS ......................................................................................................................... 85
2
OS ........................................................................................................... 86
2
OS) .......................................................................... 78
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