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17.3.2 Control Status Register 2 (ADCS2)
The control status register 2 (ADCS2) is used for A/D converter control and status
display.
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Control status register 2 (ADCS2)
The bit configuration of the control status register 2 (ADCS2) is illustrated below.
ADCS2
Address: 000047
The function of each bit of the control status register 2 (ADCS2) is described below.
[bit15] BUSY: busy flag and stop
•
During reading: This bit indicates A/D converter operation. It is set when A/D conversion
•
During writing: Setting this bit by writing "0" during A/D operation will forcibly stop operation.
When the bit is used for operation display, it cannot be set by writing "1". RMW-instructions
will always read "1". In single mode, this bit is cleared when A/D conversion ends. In
continuous and stop mode, the bit is not cleared until operation is stopped by writing "0".
This bit is initialized to "0" at reset.
Note:
Do not execute forced stop and software start simultaneously. (BUSY = 0, STRT = 1)
[bit14] INT: Interrupt
This bit is a data indication bit. This bit will be set when conversion data is written to the
ADCR.
Setting this bit when bit5 (INTE) is "1" generates an interrupt request. If μDMAC start is
enabled, μDMAC will be started. Writing "1" has no effect. Write "0" and use a μDMAC
interrupt clear signal to clear.
Initialized to "0" at reset.
Also read the Caution when using the conversion data protection function in Section "17.6
Conversion Data Protection Function of 8/10-Bit A/D Converter".
Note:
Clear this bit by writing "0"only while A/D conversion is not being performed.
15
14
13
bit
BUSY INT
INTE PAUS STS1 STS0 STRT Reserved
H
0
0
0
R/W
R/W
R/W R/W R/W
starts and cleared when A/D conversion ends.
Use this bit to force stopping in continuous mode or stop mode.
CHAPTER 17 8/10-BIT A/D CONVERTER
12
11
10
9
0
0
0
0
R/W
W
8
0
Initial value
R/W
Bit attribute
363
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