Watch Timer Control Register (Wtc) - Fujitsu MB90480 Series Hardware Manual

CHAPTER 11 WATCH TIMER

11.3 Watch Timer Control Register (WTC)

The watch timer control register (WTC) controls operation of the watch timer. This
register also controls the time of interval interrupts.
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Configuration of watch timer control register (WTC)
Figure 11.3-1 shows the configuration of the watch timer control register (WTC), and Table
11.3-1 lists the functions of bits in the watch timer control register (WTC).
Figure 11.3-1 Configuration of watch timer control register (WTC)
Address bit15
0000AA
H
R/W : Readable/Writable
R : Read only
: Default value
212
bit8 bit7 bit6 bit5 bit4
WDCS SCE WTIE WTOF
R/W R R/W R/W
WTC2 WTC1 WTC0
WTR
WTOF
WTIE
SCE
WDCS
bit3 bit2 bit1 bit0
WTR WTC2 WTC1 WTC0
R/W R/W R/W R/W
Watch timer interval selection bit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 Setting is prohibited
Watch counter clear bit
0 All bits of the watch timer counter are cleared to "0."
1 Nothing happens. This bit is always read during reading.
Watch timer interrupt request flag bit
0 No interrupt request is generated.
1 An interrupt request is generated.
Watch timer interval interrupt permit bit
0 Interrupt prohibited.
1
Interrupt permitted.
Bit indicating end of waiting time to stable
oscillation of sub-clock
0
The waiting time to stable oscillation is ongoing.
1
The waiting time to stable oscillation has ended.
Watchdog timer clock source selection bit
0 Select the clock for the watch timer
1 Select the clock for the timebase timer.
Initial value
10001000
B
Interval time
(sub-clock 32 kHz)
31.25 ms
62.5 ms
1 25 ms
250 ms
500 ms
1.000 s
2.000 s