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Operation of timebase timer
Operations in the following states are shown in Figure 9.5-2:
•
Where the power-on reset has occurred
•
Where transition to the sleep mode has occurred during processing for the interval timer
function
•
Where transition to the stop mode has occurred
•
Where clearing of the counter is requested
Transition to the stop mode clears the timebase timer to stop operation. After restoration from
the stop mode, the timebase timer starts an up-count of the oscillation stabilization wait time.
Counter value
3FFFF
Overflow during
oscillation stabilization
wait time
00000
Power-on reset
(option)
TBOF bit
TBIE bit
SLP bit
(LPMCR register)
STP bit
(LPMCR register)
"11
" is set to the interval time selection bit (TBTC; TBC1, TBC0)
B
in the timebase timer control register (2
: Oscillation stabilization wait time
HCLK : Oscillation clock
Figure 9.5-2 Operation of timebase timer
H
H
Interval cycle
Start of CPU
(TBTC : TBC1, TBC0 = 11
operation
Clearing by the interrupt
Release of interval interrupt sleep
19
/HCLK).
Clearing by transition
to stop mode
)
B
processing routine
Sleep
Stoppage
Release of stoppage
by external interrupt
CHAPTER 9 TIMEBASE TIMER
Clearing of counter
(TBTC : TBR = 0)
195
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