Fujitsu MB90480 Series Hardware Manual page 90

CHAPTER 3 INTERRUPT
μDMAC enable register (DER) has the bit functions listed below.
ENx bit
0
(Initial value)
1
Note:
Please shift to the mode after setting "0000
stand-by mode (sleep mode, stop mode, watch mode, timebase timer mode) or (main clock
intermittent operation mode, PLL clock intermittent operation mode, sub-clock intermittent
operation mode).
❍ μDMAC stop status register (DSSR)
The bit configuration of the μDMAC stop status register (DSSR) is shown below.
bit
7
0000A4 STP7
H
R/W
R/W : Readable/Writable
The function of each bit in the μDMAC stop status register (DSSR) is shown below.
STPx bit
0
(Initial value)
1
❍ μDMAC status register (DSR)
The bit configuration of the μDMAC status register (DSR) is shown below.
15
bit
00009D DE15
H
R/W
bit 7
00009C
DE7
H
R/W
R/W : Readable/Writable
68
Outputs an interrupt request from a resource to the interrupt controller.
(An interrupt request from a resource is not used as a DMA start request).
An interrupt request output from a resource is used as a DMA start request.
Cleared to "0" when the DMA transfer byte count reaches "0".
6 5 4
STP6 STP5 STP4 STP3
R/W R/W R/W
No STOP request is accepted in a DMA transfer.
STOP request is accepted in a DMA transfer to stop DMA operation.
STOP request is accepted the UART receive (channels 7) only.
The bits other than the bit7 are not valid.
Writing "1" by running software is not valid.
14 13 12 11
DE14 DE13 DE12 DE11
R/W R/W R/W R/W
6 5 4 3
DE6 DE5 DE4 DE3
R/W R/W R/W R/W
Function
" to DMA enable register (DER) whenever shifting to
H
3 2 1
STP2 STP1 STP0
R/W R/W R/W R/W
Function
10 9 8
DE10 DE9 DE8
R/W R/W R/W
2 1 0
DE2 DE1 DE0
R/W R/W R/W
0
DSSR
Initial value 00000000
DSRH
Initial value 00000000
B
DSRL
Initial value 00000000
B
B