Address Detection Control Register (Pacsr) - Fujitsu F2MC-16LX Hardware Manual

24.3.1 Address Detection Control Register (PACSR)

The address detection control register (PACSR) enables or disables output of an
interrupt at an address match. When an address match is detected when output of an
interrupt at an address match is enabled, the INT9 interrupt is generated.
I Address Detection Control Register (PACSR)
Figure 24.3-2 Address Detection Control Register (PACSR)
7 6 5
R/W R/W R/W
R/W : Read/Write
: Reset value
4 3 2 1 0
R/W R/W R/W R/W R/W
bit 0
Reserved
0
bit 1
AD0E
0
1
bit 2
Reserved
0
bit 3
AD1E
0
1
bit 4
Reserved
0
bit 5
Reserved
0
bit 6
Reserved
0
bit 7
Reserved
0
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION
Reset value
Address
0 0 0 0 0 0 0 0 009E
B
Reserved bit
Always set to "0"
Address match detection enable bit 0
Disables address match detection in PADR0
Enables address match detection in PADR0
Reserved bit
Always set to "0"
Address match detection enable bit 1
Disables address match detection in PADR1
Enables address match detection in PADR1
Reserved bit
Always set to "0"
Reserved bit
Always set to "0"
Reserved bit
Always set to "0"
Reserved bit
Always set to "0"
H
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