Configuration Of Registers For Address Match Detection Function - Fujitsu MB90480 Series Hardware Manual

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
21.3 Configuration of Registers for Address Match Detection
Function
This section details the registers used by the address match detection function.
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List of Registers and Initial Values of Address Match Detection Function
Figure 21.3-1 List of Registers and Initial Values of Address Match Detection Function
Program address detection control status register
(PACSR): Address 009E
Program address detection register 0
(PADR0): High Address 1FF2
Program address detection register 0
(PADR0): Middle Address 1FF1
Program address detection register 0
(PADR0): Low Address 1FF0
Program address detection register 1
(PADR1): High Address 1FF5
Program address detection register 1
(PADR1): Middle Address 1FF4
Program address detection register 1
(PADR1): Low Address 1FF3
×
: Undefined
460
bit
H
bit
H
bit
H
bit
H
bit
H
bit
H
bit
H
7 6 5 4 3
0 0 0 0 0
7 6 5 4 3
× × × × ×
15 14 13 12 11
× × × × ×
7 6 5 4 3
× × × × ×
7 6 5 4 3
× × × × ×
15 14 13 12 11
× × × × ×
7 6 5 4 3
× × × × ×
2 1 0
0 0 0
2 1 0
× × ×
10 9 8
× × ×
2 1 0
× × ×
2 1 0
× × ×
10 9 8
× × ×
2 1 0
× × ×