Program Address Detection Control Status Register (Pacsr) - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
21.3.1 Program Address Detection Control Status Register
(PACSR)
The program address detection control status register (PACSR) enables or disables
output of an interrupt at an address match. When an address match is detected when
output of an interrupt at an address match is enabled, the INT9 interrupt is generated.

■ Program Address Detection Control Status Register (PACSR)

Figure 21.3-2 Program Address Detection Control Status Register (PACSR)
bit 7 6
Address
Reserved Reserved Reserved Reserved
009E
H
R/W R/W
R/W : Readable/Writable
: Initial value
CM44-10137-6E
5 4 3 2 1 0
AD1E AD0E
Reserved Reserved
R/W R/W R/W R/W R/W R/W
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
21.3 Configuration of Address Match Detection Function
Initial value
00000000
B
bit 0
Reserved bit
Reserved
0 Always set to "0"
bit 1
Address match detection enable bit 0
AD0E
0
Disables address match detection in PADR0
1
Enables address match detection in PADR0
bit 2
Reserved bit
Reserved
0 Always set to "0"
bit 3
AD1E Address match detection enable bit 1
0 Disables address match detection in PADR1
1
Enables address match detection in PADR1
bit 4
Reserved bit
Reserved
Always set to "0"
0
bit 5
Reserved bit
Reserved
0 Always set to "0"
bit 6
Reserved bit
Reserved
0 Always set to "0"
bit 7
Reserved bit
Reserved
Always set to "0"
0
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