Fujitsu MB90480 Series Hardware Manual page 142

CHAPTER 5 CLOCKS
(1) MCS bit "0" write
(2) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 00
(3) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 01
(4) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 10
(5) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 11
(6) MCS bit "1" write (includes watchdog reset)
(7) Synchronization timing of PLL and main clocks
(8) SCS bit "0" write
(9) End of waiting time for sub-clock oscillation stability (maximum 2
(10) SCS bit "1" write
(11) Waiting for main clock oscillation stability is complete.
(12) Waiting for main clock oscillation stability is complete. &CS1, CS0 = 00
(13) Waiting for main clock oscillation stability is complete. &CS1, CS0 = 01
(14) Waiting for main clock oscillation stability is complete. &CS1, CS0 = 10
(15) Waiting for main clock oscillation stability is complete. &CS1, CS0 = 11
(16) SCS bit "1" write, MCS bit "0" write
(17) Synchronization timing of PLL and sub-clocks
MCS: PLL clock selection bit of clock selection register (CKSCR)
MCM: PLL clock display bit of clock selection register (CKSCR)
SCS: Sub-clock selection bit of clock selection register (CKSCR)
SCM: Sub-clock display bit of clock selection register (CKSCR)
CS1, CS0: Multiplication rate selection bit of clock selection register (CKSCR)
Note:
The initial value of the machine clocks is the main clock (MCS = 1, SCS = 1).
If both of the SCS and MCS bits are "0", SCS is assigned with priority and the sub-clock is set.
When sub-clock mode is switched to PLL clock mode, set "10
stabilization wait time selection bits (WS1, WS0) of the CKSCR register.
120
14
/SCLK)
" or "11 " in the oscillation
B B