Interrupt Of 8/10-Bit A/D Converter - Fujitsu MB90480 Series Hardware Manual

17.4

Interrupt of 8/10-Bit A/D Converter

The 8/10-Bit A/D converter generates the interrupt request when the A/D conversion is
terminated, and the conversion result is stored to the A/D data register (ADCR). Also, it
can activate the DMA transfer and extended intelligent I/O service (EI
■
Interrupt of 8/10-bit A/D converter
The interrupt control bit and the interrupt source of the 8/10-bit A/D converter is shown in the
following table.
Interrupt request flag
Interrupt request output enable bit
Interrupt generation source
■
Interrupt of A/D converter
When A/D conversion of the analog input voltage is terminated and its results are stored in the
data register (ADCR), the interrupt request flag bit in the A/D control status register (ADCS: INT)
is set to "1". Interrupt request is generated when the interrupt request flag bit (ADCS: INT=1) is
set with interrupt request output enabled (ADCS: INTE=1).
■
Interrupt of 8/10-bit A/D converter, DMA transfer, and EI
Table 17.4-1 shows the relationship between the interrupt source, interrupt vector, and interrupt
control register other than software interrupt.
Table 17.4-1 Interrupt source, interrupt vector, and interrupt control register
Interrupt source
❍
Interrupt request flag is cleared.
:
This interrupt source shares the interrupt source and interrupt number of other peripheral
* :
function.
For details, see Table 3.2-2.
Note:
If there are two interrupt sources in the same interrupt number, resource clears both interrupt
request flags. Therefore, when one of two sources uses the EI
interrupt function cannot use. The interrupt request enable bit of the relevant resource is set to 0 to
execute the software polling processing..
■
Correspondence to DMA transfer and EI
The interrupt of the A/D converter corresponds to the DMA transfer function and EI
the DMA or EI
interrupt control register (ICR).
A/D converter*
2
OS function is used, it is necessary to disable other interrupt that shares the
CHAPTER 17 8/10-BIT A/D CONVERTER
ADCS:INT (bit14)
ADCS:INTE (bit13)
A/D conversion result is stored to A/D data register
(ADCR).
μDMAC
Interrupt vector
2
EI OS
channel
clear
Number
number
❍
15 #40
2
OS function
2
OS).
2
OS
Interrupt control register
Address Number
FFFF5C
ICR14
H
2
OS/μDMAC function, the other
2
OS function. When
Address
0000BE
H
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