Fujitsu MB90480 Series Hardware Manual page 673

Block diagram of pin related to I
Block diagram of pin related to μPG timer
Block diagram of pin related to PWC timer
Block diagram of pin related to UART
Block diagram of PWC timer
Block diagram of the 16-bit reload timer
Block diagram of the 8/16-bit PPG timer
Block diagram of the chip selection facility
2
Block diagram of the I C interface
Block diagram of the ROM mirror function selection
................................................ 474
module
Block diagram of timebase timer
Block diagram of watch timer
Block diagram of watchdog timer
......................................... 409
UART Block Diagram
Buffer
Buffer address pointer (BAP)
Bus
.......................................................... 575
Bus error
Bus status register (IBSR)
Notes on using the bus control register (IBCR)
Bus control
Bus control register (IBCR)
Bus control signal selection register (EPCR)
Bus mode
Bus mode setting bit (M1,M0)
........................................................ 154
Bus modes
C
CALR
Chip selection active level register (CALR)
CARx
Chip selection area register (CARx)
CCR
Condition code register (CCR)
CCRH
Counter control register (ch0) upper (CCRH0)
Counter control register (ch1) upper (CCRH1)
CCRL
Counter control register (ch0/ch1) lower
........................................... 269
(CCRL0/1)
CDCR
Communication prescaler control register
............................................... 419
(CDCR)
Chip
Chip/sector erase operation
Write/chip sector erase operation
Write/chip sector erase operations
Chip erase
Erasing all data in the flash memory (chip erase)
Chip select
Block diagram of pin related to chip select
................................................ 448
facility
Chip selection
Block diagram of the chip selection facility
Chip selection active level register (CALR)
Chip selection area MASK register (CMRx)
2
............. 558
C interface
................ 551
............... 518
.................... 410
................................ 517
.................. 294
.................. 319
.............. 447
.......................... 557
............................ 188
................................ 211
........................... 203
............................ 74, 84
..................................... 560
.......... 567
.................................. 562
............. 165
............................... 157
.............. 453
........................ 451
................................. 33
.......... 265
.......... 267
................................... 489
............................ 492
.......................... 491
........ 498
.............. 447
.............. 453
............. 450
Chip selection area register (CARx)
Chip selection control register (CSCR)
Example of using the chip selection facility
List of registers used for the chip selection
.................................................449
facility
Notes on using the chip selection facility
Overview of the chip selection facility
Pin related to chip selection facility
Circuit type
.....................................................18
I/O circuit type
CKSCR
Configuration of clock selection register
.............................................112
(CKSCR)
Clear
Count clear/gate function
Clearing
.............................................283
Clearing the counter
................................................537
Clearing the timer
CLK
Operation in CLK synchronous mode
(operation mode 2)
Clock
Block diagram of clock generator
Clock control register (ICCR)
Clock source for watchdog timer specifying
...............................................215
function
................................................109
Clock supply map
Clock supplying function
Configuration of clock selection register
.............................................112
(CKSCR)
...........................................533
Count clock selection
.............................................292
Internal clock mode
Oscillation clock frequency and serial clock input
.............................................508
frequency
..............................................108
Overview of clocks
..........................................424
UART clock selection
Clock mode
..........................................117
Change of clock mode
Switching the clock mode
......................................................125
Clock modes
CMR
Common register bank prefix (CMR)
CMRx
Chip selection area MASK register (CMRx)
Code
..........................................42
Continuous prefix codes
Command sequence
Command sequence table
Common
Common register bank prefix (CMR)
Communication prescaler
Communication prescaler control register
...............................................419
(CDCR)
Communication prescaler control register0/1
(SDCR0/SDCR1)
Compare
Compare clear register (CPCLR)
................................................281
Compare function
.........................451
.....................452
...............454
..................455
.....................446
.........................447
......................................283
.................................430
............................110
................................568
..............................187, 194
.....................................149
.........................41
..............450
......................................486
.........................41
...................................395
............................224
651