Fujitsu MB90480 Series Hardware Manual page 258

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
request occurs.
● Output compare interrupt
The interrupt operation when a match between the count value of the free-running timer and the
setting value of the compare register is detected is shown as follows:
• The output compare match flag in the control register is set to 1 (OCS:IOP=1).
• When the output compare interrupt request is set to enable (OCS: IOE=1), the interrupt
request occurs.
■
Interrupt of 16-bit input/output timer, DMA transfer, and EI
Table 12.4-2 shows the relationship between the interrupt source, interrupt vector, and interrupt
control register other than software interrupt.
Table 12.4-2 Interrupt source, interrupt vector, and interrupt control register
Interrupt source
Input capture (channel 0) fetch
Input capture (channel 1) fetch
Output compare (channel 0) match
Output compare (channel 1) match
Output compare (channel 2) match
Output compare (channel 3) match
Output compare (channel 4) match
Output compare (channel 5) match
16-bit free-running timer overflow,
16-bit reload timer underflow
×
: Interrupt request flag is not cleared.
❍ : Interrupt request flag is cleared.
* : This interrupt source shares the interrupt source and interrupt number of other peripheral function.
For details, see Table 3.2-2.
Note:
If there are two interrupt sources in the same interrupt number, resource clears both interrupt request flags.
Therefore, when one of two sources uses the EI
used. The interrupt request enable bit of the relevant resource is set to "0" to execute the software polling
processing.
■
Correspondence to DMA transfer and EI
The input capture and free-running timer correspond to the DMA transfer and EI
The output compare corresponds to the DMA transfer function only for EI
to ch.2. When the DMA or EI
shares the interrupt control register (ICR).
236
2
EI OS
clear
❍
*
❍
❍
❍
❍
❍
❍
❍
*
*
❍
2
OS function is used, it is necessary to disable other interrupt that
2
OS
μDMAC
Interrupt vector
channel
Number Address
number
FFFF94
5 #26
FFFF90
6 #27
FFFF8C
8 #28
FFFF88
9 #29
FFFF84
10 #30
×
FFFF80
#31
×
FFFF7C
#32
×
FFFF78
#33
FFFF70
12 #35
2
OS/μDMAC function, other interrupt function cannot be
2
OS function
Interrupt control register
Number Address
0000B7
ICR07
H H
H
0000B8
ICR08
H
H
H
0000B9
ICR09
H
H
H
0000BA
ICR10
H
H
0000BB
ICR11
H H
0000BC
ICR12
H H
2
OS functions.
2
OS function and ch.0