Fujitsu MB90480 Series Hardware Manual page 573

Block diagram of pin related to μPG timer
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Port data register (PDR)
PDR Read
PDR Write
Port direction register
DDR Write
DDR Read
Standby control : Stop mode (SPL=1), timebase timer mode (SPL=1), watch mode (SPL=1)
Figure 26.1-2 Block diagram of pin related to μPG timer
Peripheral
function input
Output latch
(DDR)
Direction latch
CHAPTER 26 μPG TIMER (ONLY MB90485 SERIES)
Peripheral function output
(MT00, MT01)
(EXTC)
Peripheral function output enable
Standby control (SPL=1)
Open drain control signal
(P43/P44/P45 only)
P-ch
Pin
N-ch
551