Fujitsu MB90480 Series Hardware Manual page 597

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Acknowledge
Acknowledge is transmitted from the receiving side to the transmitting side. The ACK bit is used
to represent an acknowledge upon data reception. If data is transmitted, an acknowledge from
the receive side is stored in the LRB bit.
If no acknowledge is received from the master side (receiving device) after reception from the
slave (transmitting side), the TRX bit is set to "0" and the device enters slave reception state.
The master device will in this case generate a stop condition when the slave opens the SCL
line.
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Bus error
If the following conditions are satisfied, it can be assumed that a bus error occurred, and the I
interface will enter stop mode.
• If an I
included).
• If a stop condition is detected in master mode
• If an I
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Other considerations
❍ Processing after arbitration lost is detected
When arbitration lost is detected, the software has to determine whether local addressing was
applied.
If arbitration lost occurs, the device enters slave mode on the hardware level, and after 1-byte
transfer has been completed, both the CLK line and DATA line are set to "L" level.
Consequently, without proper addressing, both the CLK line and DATA line will be immediately
opened. With addressing, slave transmission or slave reception will have been set up before the
CLK line and DATA line are opened (all of these preparations must be performed by software).
❍ Interrupt sources when arbitration lost is detected
If arbitration lost is detected, an interrupt source is not generated immediately, but only after the
transfer of one byte is completed.
If arbitration lost is detected, the device enters slave mode on the hardware level. Even if this
occurs in slave mode, a total of nine clocks will be output before the interrupt source is
generated. Since interrupt sources are not generated immediately, no interrupt processing is
performed after arbitration lost occurs.
2
C bus basic standard violation is detected in data transfer mode (when an ACK bit is
2
C bus basic standard violation is detected in bus idle mode.
2
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES)
2
C
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