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CHAPTER 4 RESET
■
Correspondence between reset-factor bits and reset factors
Figure 4.5-2 shows the configuration of the reset-factor bits for the watchdog timer control
register (WDTC). Table 4.5-1 shows the correspondence between reset-factor bits and reset
factors.
For details, refer to Section "10.2 Watchdog Timer Control Register (WDTC)".
Figure 4.5-2 Configuration of reset-factor bits (watchdog timer control register)
bit
15 - - - - - - - 8
0000A8
(TBTC)
H
R: Read only; W: Write only
Table 4.5-1 Correspondence between reset-factor bits and reset factors
Power-on reset
Watchdog timer overflow
External reset request via pin RST
Software reset request
* : Retains the state before
X: Undefined bit
■
Cautions about reset-factor bits
❍ If more than one reset factor occurs
If more than one reset factor occurs, the individual reset-factor bits of the WDTC register are set
to "1". For example, if an external reset via pin RST is requested at the same time as a
watchdog timer overflow occurs, bits ERST and WRST of the reset-factor bits are set to "1".
❍ Power-on reset
During a power-on reset, bit PONR of the reset-factor bits is set to "1". However, the reset-factor
bits other than bit PONR are undefined. Therefore, if bit PONR is "1", create software so that
reset-factor bits other than bit PONR are ignored.
❍ Clearing reset-factor bits
The reset-factor bits is cleared only if the data in the WDTC register is read. Bits corresponding
to reset factors that have occurred once are not cleared even if a reset is triggered (remains
"1").
Note:
The values of the WDTC register may not be assured if the power is turned on under a condition
that precludes a power-on reset.
104
7
6
5
PONR Reserved
WRST ERST
X
X
X
R
R
R
Reset factor
4
3
2
SRST
WTE
WT1
X
X
1
R
R
W
PONR
WRST
1
X
*
1
*
*
*
*
1
0
WT0
1
1
Initial value
W
W
R/W
ERST
SRST
X
X
*
*
1
*
*
1
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