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CHAPTER 3 INTERRUPT
Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers (2 / 2)
Interrupt factor
Output compare (ch.5) match
UART transmit completed
16-bit free-running timer overflow
16-bit reload timer underflow
UART receive completed
SI01(ch.0)
SI02(ch.1)
2
I
C interface (Only MB90485 series)
A/D converter
FLASH write/delete, timebase timer,
*1
watch timer
Delay interrupt generation module
x: The interrupt request flag cannot be cleared by the interrupt clear signal.
❍: The interrupt request flag is cleared.
:The interrupt request flag is cleared. The stop request is provided.
*1: Caution: The FLASH write/erase, timebase timer, and watch timer cannot be used at the same time.
*2: Please write "0" in the INTE bit, after prohibiting interrupt by setting the IL2 bit to IL0 bit of the interrupt
control register to "111
TMCSR registers =1) to prohibit (INTE bit of TMCSR registers =0).
Note:
If there are two interruption factors to the same interruption number, both interrupt request flag is
cleared by interrupt clear signal on the resource. Therefore, when one of two factors uses the
2
OS function or the μDMAC function, the other interrupt function cannot be used. Set the
EI
interruption request permission bit of the corresponding resource to "0" and handle with software
polling processing.
48
2
EI
OS
clear
❍
❍
❍
*2
❍
❍
×
❍
❍
×
", if the reload timer underflow interrupt setting is changed from enable (INTE bit of
B
μDMAC
Interrupt vector
channel
number
Number
Address
×
#33
FFFF78
11
#34
FFFF74
FFFF70
12
#35
7
#36
FFFF6C
13
#37
FFFF68
14
#38
FFFF64
×
#39
FFFF60
15
#40
FFFF5C
×
#41
FFFF58
×
#42
FFFF54
Interrupt control
register
Number
Address
H
ICR11
0000BB
H
H
ICR12
0000BC
H
H
ICR13
0000BD
H
H
ICR14
0000BE
H
H
ICR15
0000BF
H
H
H
H
H
H
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