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Notes on using the bus control register (IBCR)
Setting the SCC bit to "1" and the MSS bit to "0" at the same time is prohibited.
Writing to the SCC, MSS, and INT bits at the same time will cause a conflict between transfer of
the next byte and generation of start or stop conditions. In this case, the priority is specified as
follows.
❍ Next byte transfer and stop condition generation
If the INT and MSS bits are set to "0", setting of the MSS bit to "0" has priority and the stop
condition is generated.
❍ Next byte transfer and start condition generation
If the INT bit is set to "0" and the SCC bit is set to "1", setting of the SCC bit to "1" has priority
and the start condition is generated.
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CHAPTER 27 I
C INTERFACE (ONLY MB90485 SERIES)
567
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