Appendix B I/O Map - Fujitsu MB90480 Series Hardware Manual

APPENDIX B I/O Map

Table B-1 shows the addresses assigned to the registers for each peripheral function.
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I/O maps
Table B-1 shows the addresses assigned to the registers for each peripheral function.
Table B-1 I/O Map (1/8)
Address
00 Port 0 data register
H
01 Port 1 data register
H
02 Port 2 data register
H
03 Port 3 data register
H
04 Port 4 data register
H
05 Port 5 data register
H
06 Port 6 data register
H
07 Port 7 data register
H
08 Port 8 data register
H
09 Port 9 data register
H
0A Port A data register
H
Up/down timer input enable
0B
H
register
0C Interrupt/DTP enable register
H
0D Interrupt/DTP enable register
H
0E Request level setting register
H
0F Request level setting register
H
10 Port 0 direction register
H
11 Port 1 direction register
H
12 Port 2 direction register
H
13 Port 3 direction register
H
14 Port 4 direction register
H
15 Port 5 direction register
H
16 Port 6 direction register
H
Register Abbreviation Access
PDR0 R/W
PDR1 R/W
PDR2 R/W
PDR3 R/W
PDR4 R/W
PDR5 R/W
PDR6 R/W
PDR7 R/W
PDR8 R/W
PDR9 R/W
PDRA R/W
UDRE R/W
ENIR R/W
EIRR R/W
R/W
ELVR
R/W
DDR0 R/W
DDR1 R/W
DDR2 R/W
DDR3 R/W
DDR4 R/W
DDR5 R/W
DDR6 R/W
APPENDIX B I/O Map
Resource Initial value
Port 0 XXXXXXXX
Port 1 XXXXXXXX
Port 2 XXXXXXXX
Port 3 XXXXXXXX
Port 4 XXXXXXXX
Port 5 XXXXXXXX
Port 6 XXXXXXXX
XXXXXXXX
(MB90480
series)
Port 7
11XXXXXX
(MB90485
series)
Port 8 XXXXXXXX
Port 9 XXXXXXXX
Port A ----XXXX
Up/down timer
XX000000
input control
00000000
XXXXXXXX
DTP/external
interrupt
00000000
00000000
Port 0 00000000
Port 1 00000000
Port 2 00000000
Port 3 00000000
Port 4 00000000
Port 5 00000000
Port 6 00000000
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
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