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CHAPTER 7 MODE SETTING
7.5.3
Hold function
This section uses timing charts to describe the operation of the hold function.
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Operation of hold function
When the HDE bit of EPCR is set to "1", the external bus hold function specified by both the
P54/HRQ and P55/HAK pins becomes effective. When the "H" level is input to the P54/HRQ
pin, the hold state is set upon completion of a command by the CPU (after data of 1 element is
processed in the case of the string command), and the "L" level is output from P55/HAK to set
the following pins to a high-impedance state:
❍ Non-multiplex mode
•
Address output: A23 to A00
•
Data input/output: D15/AD15 to D00/AD00
•
Bus control signal: P51/RD, P52/WRL, P53/WRH
❍ Multiplex mode
•
Address output: A23 to A16
•
Address output, Data input/output: D15/AD15 to D00/AD00
•
Bus control signal: P51/RD, P52/WRL, P53/WRH
This operation enables use of the external bus via the device external circuit. When the "L" level
is input to the P54/HRQ pin, the P55/HAK pin outputs the "H" level to restore the external pin
state, and the CPU restarts operation. In the STOP state, requests for hold are rejected.
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