Data Register (Idar) - Fujitsu MB90480 Series Hardware Manual

27.3.5 Data Register (IDAR)

This section describes the configuration and functions of the data register (IDAR).
■
Data register (IDAR)
The diagram below shows the bit configuration of the data register (IDAR).
[bit7 to bit0] D7 to D0
These bits are used as data bits.
These bits constitute a data register for serial transfer starting with the MSB. If data is
received (TRX = 0), the data output value becomes "1".
With respect to writing, this register consists of a double buffer. If the bus is active (BB = 1),
write data is loaded into the register for serial transfer. When the register is directly read for
serial transfer, note that the receive data is only valid if the INT bit of the IBCR register is set.
Data register
7
Address: 00008C
H
D7
Read/Write
(R/W)(R/W)(R/W) (R/W)(R/W)(R/W)(R/W)(R/W)
Initial value
(X)
2
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES)
6 5 4 3 2
D6 D5 D4 D3 D2
(X) (X) (X) (X) (X)
1 0 Bit number
D1 D0 IDAR
(X) (X)
571