Sleep Mode - Fujitsu MB90480 Series Hardware Manual

6.5.1

Sleep Mode

The sleep mode stops CPU operation clocks, allowing devices other than the CPU to
continue operation.
■
Change to sleep mode
Writing "1" in the sleep mode bit (SLP), "1" in the watch/timebase timer mode bit (TMD), and "0"
in the stop mode bit (STP) of the low-power consumption mode control register (LPMCR)
changes the mode to the sleep mode.
Note:
If "1" is simultaneously written in the SLP and STP bits of the LPMCR register, the STP bit has the
priority and the device is changed to the stop mode.
If writing "1" in the SLP bit and writing "0" in the TMD bit of the low-power consumption mode
control register are performed at the same time, the TMD bit has the priority and the device is
changed to the timebase timer mode or watch mode.
❍ Data hold function
This function in the sleep mode holds data of the internal RAM and dedicated registers such as
an accumulator.
❍ Hold function
The external bus hold function operates in the sleep mode. A hold state is set if a hold request
is issued.
❍ Operation during interrupt request
The sleep mode is not set if an interrupt request is issued while "1" is written in the SLP bit of
the LPMCR register. The CPU executes a next instruction if an interrupt request is not
accepted. If the CPU can accept an interrupt request, the request is immediately branched to an
interrupt processing routine.
❍ Pin state
In the sleep mode, the previous states are maintained except for pins used for bus input and
output or for bus control.
CHAPTER 6 LOW-POWER CONSUMPTION MODE
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