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CHAPTER 19 UART
❍ Reception Operation
Reception is always performed if reception operation is enabled (SCR: RXE = 1). When the
start bit is detected, one frame of data is received in accordance with the data format
determined by the serial control register (SCR). When the error flag is set at the time of error
after one frame has been received, the reception data full flag bit (SSR: RDRF) is set to "1". If
reception interrupt requests are enabled (SSR: RIE = 1), a reception interrupt request is output
in this case. Each flag of the serial status register (SSR) is checked. If reception was performed
normally, the serial input register (SIDR) is read; if an error is detected, perform error
processing.
The RDRF flag is cleared to "0" after reception data is read from the SIDR.
❍ Detecting the start bit
Implement the following settings to detect the start bit:
•
Set the communication line level to "H" (attach the mark level) before the communication
period.
•
Specify reception permission (RXE="H") while the communication line level is "H" (mark level).
•
Do not specify reception permission (RXE="H") for the periods other than the communication
period (without mark level).
•
After the stop bit is detected (the RDRF flag is set to "1"), specify reception inhibition (RXE =
"L") while the communication line level is "H" (mark level).
Non-communication period
SIN
(Sending 01010101
)
B
RXE
Receive clock
Sampling clock
Recognition by the microcontroller
(Receiving 01010101
)
B
Note that specifying reception permission at the timing shown below obstructs the correct
recognition of the input data (SIN) by the microcontroller.
•
Example of operation if reception permission (RXE="H") is specified while the communication
line level is "L".
Non-communication period
SIN
(Sending 01010101
)
B
RXE
Receive clock
Sampling clock
Recognition by the microcontroller
(Receiving 10101010
)
B
PE,ORE,FRE
428
Figure 19.5-2 Normal operation
Mark level
Start bit
ST
D1
D0
Receive clock (8 pulse)
Generating sampling clocks by dividing the receive clock by 16
ST
D1
D0
Figure 19.5-3 Error operation
Mark level
Start bit
ST
D1
D0
ST recognition
D0
D2
D1
Communication period
Data
D5
D3
D2
D4
D6
D3
D5
D2
D4
D6
Communication period
Data
D3
D5
D2
D4
D6
D4
D6
D3
D5
D7
Occurrence of a reception error
Non-communication period
Stop bit
D7
SP
D7
SP
Non-communication period
Stop bit
D7
SP
SP
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