Fujitsu MB90480 Series Hardware Manual page 312

F2mc-16lx 16-bit microcontroller
Table of Contents

Advertisement

CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
● Method to set reload value and compare value
Set the value to the reload/compare registers (RCR0, RCR1) (same value is set for compare
value and reload value).
● Interrupt related register
The relationship between the up/down counter number, interrupt level, and interrupt vector is
shown in the following table.
For details of the interrupt level and interrupt vector, see CHAPTER 3 INTERRUPT.
Up/down counter
Interrupt request flag
Count direction reversal: (CCR0.CDCF), (CCR1.CDCF)
Compare detection:
Overflow:
Underflow:
The above interrupt request flag does not clear automatically. Write "0" to the interrupt request
flag with software before returning from the interrupt processing.
● Type of interrupt and selection method
The following three interrupt sources are provided:
count direction reversal, match of comparison result, overflow/underflow
The interrupt occurs with OR of the above three interrupt sources. The interrupt source is
selected by the interrupt request enable bit.
● Method to enable (select)/disable/clear interrupt
Enabling (selecting)/disabling interrupt sets using the interrupt request enable bits below:
Count direction reversal interrupt request enable bit: (CCR0.CFIE), (CCR1.CFIE)
Compare interrupt request enable bit
Overflow/underflow interrupt request enable bit
To disable interrupt request
To enable interrupt request
Clearing interrupt request sets using the interrupt request bits below:
Count direction reversal: (CCR0.CDCF), (CCR1.CDCF)
Compare detection
Overflow
Underflow
To clear interrupt request
290
Source
Interrupt vector
Address : FFFF98
(CSR0.CMPF), (CSR1.CMPF)
(CSR0.OVFF), (CSR1.OVFF)
(CSR0.UDFF), (CSR1.UDFF)
Control
: (CSR0.CMPF), (CSR1.CMPF)
: (CSR0.OVFF), (CSR1.OVFF)
: (CSR0.UDFF), (CSR1.UDFF)
Control
Interrupt level setting register
#25
Interrupt level register (ICR07)
H
: (CSR0.CITE), (CSR1.CITE)
: (CSR0.UDIE), (CSR1.UDIE)
Interrupt request enable bit (CFIE, CITE, UDIE)
Set to "0"
Set to "1"
Interrupt request bits (CDCF, CMPF, OVFF, UDFF)
Write "0"
Address : 0000B7
H

Advertisement

Table of Contents
loading

Table of Contents