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CHAPTER 20 CHIP SELECTION FACILITY
20.3.3 Chip Selection Control Register (CSCR)
This section describes the configuration and functions of the chip selection control
register (CSCR).
■
Chip selection control register (CSCR)
The diagram below shows the bit configuration of the chip selection control register (CSCR).
0000C8
H
(-)
(-)
* : The initial value of this bit is "1" or "0". The value depends on the mode pins (MD2, MD1, MD0 pins).
[bit7 to bit4] Unused bits
These bits are unused. In read operations, the return value for these bits is undefined.
[bit3 to bit0] OPL3 to OPL0
These bits are used to specify whether CS3 to CS0 are output to the external pin.
The operational settings are as follows:
•
"0": Decode output from each CS3 to CS0 pin is prohibited
•
"1": Decode output from each CS3 to CS0 pin is allowed
Notes:
• The initial value of OPL0 is set to "1" in external vector mode, and set to "0" in internal vector
mode.
• Enabling CS3 to CS0 output must be performed after all settings have been made.
• Change settings during operation only after prohibiting OPL3 to OPL0 to output.
452
7
6
5
4
-
-
-
-
(-)
(-)
(-)
(-)
(-)
(-)
3
2
1
0
OPL3 OPL2 OPL1 OPL0
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(*)
CSCR
Chip selection control register
Read/Write
Initial value
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