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13.3.3 Counter control register (ch.0/ch.1) lower (CCRL0/CCRL1)
This section describes the configuration and explains the function of counter control
register (ch.0/ch.1) lower (CCRL0/CCRL1).
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Counter control register (ch.0/ch.1) lower (CCRL0/CCRL1)
The bit configuration of counter control register (ch.0/ch.1) lower (CCRL0/CCRL1) is shown
below.
Figure 13.3-4 Bit configuration of counter control register (ch.0/ch.1) lower (CCRL0/CCRL1)
CCRL0
ch.0 Address: 00006C
CCRL1
ch.1 Address: 000070
Counter control register (ch.0/ch.1) lower (CCRL0/CCRL1) consists of bits that have the
functions explained below.
[bit7] UDMS (up/down mode selection)
This bit is used to control the up/down at the falling edge of the BIN pin in the phase
difference counter mode at frequency multiplied by 2.
It is initialized to "0" by a reset. Read and write operations are possible.
UDMS
0
1
If this bit is rewritten after its start, the count value is not assured.
[bit6] CTUT (counter write)
This bit is used to control data transfers from RCR to UDCR.
If this bit is set to "1", data is transferred from RCR to UDCR.
Writing "0" has no effect.
bit
7
6
5
UDMS CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
H
R/W
W
R/W R/W
H
Decremented if the AIN pin value detected at the falling edge of the BIN pin is
"H" (initial value)
Incremented if the AIN pin value detected at the falling edge of the BIN pin is "L"
(initial value)
Decremented if the AIN pin value detected at the falling edge of the BIN pin is "L"
Incremented if the AIN pin value detected at the falling edge of the BIN pin is "H"
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
4
3
2
1
W
R/W
R/W R/W
Operation
0
Initial value
0X00X000
B
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