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CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
❍ If reload or clear events are generated in a count operation
All updating operations of UDCR are in sync with the count clock. Figure 13.5-6 shows an
example of reloading 080
UDCR
Reload/clear event
Count clock
❍ If reload and clear events are generated just before the count operation stops
If counting stops in the count clock sync wait mode (state where count input is held for
synchronization), reload and clear operations are performed when the stop occurs.
Figure 13.5-7 shows an example of reloading 080
Figure 13.5-7 Count stop operation in count clock sync signal wait mode
UDCR
Reload/clear event
Count clock
Count enable
❍ If reload and clear events are generated in the count stop mode
Update of UDCR is performed when an event occurs.
Figure 13.5-8 shows an example of reloading "080
Figure 13.5-8 Operation when reload/clear event occurs in count stop mode
UDCR
Reload/clear event
❍ If counter is cleared by the comparison result match
A clear operation caused by compare is performed if the UDCR and RCR values match and
incrementing (up count) occurs. Even if the UDCR and RCR values match, no clear operation is
performed if a down-count or count stop occurs subsequently.
A clear operation is performed at the above timing for all events other than reset input. Reload is
also performed at the above timing in any event.
If clear and reload events occur at the same time, the clear event has priority.
282
.
H
Figure 13.5-6 Normal operation counting
065
066
H
065
066
H
Enable (count permitted)
065
080
H
080
H
H
↓ Synchronized with this clock
.
H
080
H
H
Disable (count prohibited)
".
H
H
081
H
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