Fujitsu MB90480 Series Hardware Manual page 272

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
<Interrupt>
•
Interrupt processing
Clear interrupt request flag
(Arbitrary processing)
••••••••••
Clear interrupt request flag
(Arbitrary processing)
••••••••••
<Interrupt vector>
•
Set vector table
Note:
Setting related to clock and setting of _set_il (numeric
value) are required in advance. See the chapter of
clock and interrupt.
■
Setting method other than program example
● Method to set compare value
The compare value is written to the compare registers (OCCP0 to OCCP5).
● Method to set compare mode (valid for OUT1, OUT2, OUT3, OUT4, OUT5 output)
Set by compare mode bit (OCS01.CMOD, OCS23.CMOD, OCS45.CMOD).
To reverse OUT1 output by a match with comparison result between
free-running timer and compare register 1
To reverse OUT3 output by a match with comparison result between
free-running timer and compare register 3
To reverse OUT5 output by a match with comparison result between
free-running timer and compare register 5
To reverse Out1 output by match with comparison result between
free-running timer and compare register 0 and between free-running
timer and compare register 1
To reverse Out3 output by match with comparison result between
free-running timer and compare register 2 and between free-running
timer and compare register 3
To reverse Out5 output by match with comparison result between
free-running timer and compare register 4 and between free-running
timer and compare register 5
The following is output regardless of the CMOD bit.
• OUT0 output reverses output by a match with comparison result between free-running timer
and compare register 0.
• OUT2 output reverses output by a match with comparison result between free-running timer
and compare register 2.
250
__interrupt void OUTPUT0_int(void)
{
Register name. bit name
IO_OCS01.bit.ICP0 = 0; /* bit6 = 0
OCS01 .ICP0
• • • • • •
}
__interrupt void OUTPUT1_int(void)
{
OCS01 .ICP1 IO_OCS01.bit.ICP1 = 0; /* bit7 = 0
• • • • • •
}
#pragma intvect OUTPUT0_int 28
#pragma intvect OUTPUT1_int 29
Note:
For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR F
16LX FAMILY MB90480 SERIES".
Operation
(Continued)
Clear ICP0 interrupt flag */
Clear ICP1 interrupt flag */
2
Compare mode bit
Set (OCS01.CMOD) bit to "0"
Set (OCS23.CMOD) bit to "0"
Set (OCS45.CMOD) bit to "0"
Set (OCS01.CMOD) bit to "1"
Set (OCS23.CMOD) bit to "1"
Set (OCS45.CMOD) bit to "1"
MC-