Table of Contents
Advertisement
CHAPTER 20 CHIP SELECTION FACILITY
20.4 Operation of the Chip Selection Facility
This section describes the operations of the chip selection facility.
■
Outline of operations
When the CPU accesses program or data, the chip selection facility is activated if a match
between the upper 8 bits of an address and CAR0/1/2/3 is detected. Addresses for which the
corresponding bits in CMR0/CMR1/CMR2/CMR3 are set to "1" are ignored, and decoding
becomes possible for an area from 64 K bytes to 16 MB.
The CS pin is not set to active while CPU is performing internal access (such as built-in RAM,
built-in ROM, and built-in I/O).
■
Example of using the chip selection facility
Figure 20.4-1 shows an example of using the chip selection facility.
[Example 1]
[Example 2]
454
Figure 20.4-1 Example of using the chip selection facility
Address
11111110
Matching
CMR0
00000000
CAR0
11111110
Address
11111110
Matching
CMR0
00001111
CAR0
11111010
XXXXXXXX XXXXXXXX FEXXXXXX
CS0 active
XXXXXXXX XXXXXXXX FEXXXXXX
CS0 active
H
H
Advertisement
Table of Contents
