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15.2 Configuration of 8/16-Bit PPG Timer
This section shows the configuration of channels 0/2/4 and channels 1/3/5 of the 8/16-
bit PPG timer.
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Block diagram of the 8/16-bit PPG timer
Figure 15.2-1 shows a block diagram of channels 0, 2, and 4. Figure 15.2-2 shows a block
diagram of channels 1, 3, and 5.
Figure 15.2-1 Block diagram of the 8/16-bit PPG timer (channels 0/2/4)
Peripheral clock: divide-by-16
Peripheral clock: divide-by-8
Peripheral clock: divide-by-4
Peripheral clock: divide-by-2
Peripheral clock
Count clock
select
Timebase counter output
Main clock: divide-by-512
"L"/"H" select
PPG0/2/4 output allowed
PPG0/2/4 output latch
PCNT(down-counter)
"L"/"H" selector
PRLL
PRLBH
PRLL
CHAPTER 15 8/16-BIT PPG TIMER
PPG0/2/4
A/D converter
PEN0
S
R
Q
ch1/3/5 borrow
PUF0
PIE0
PPGC0
(operation mode control)
"L" data bus
"H" data bus
IRQ
319
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