Fujitsu MB90480 Series Hardware Manual page 367

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Interrupt/DTP source register (EIRR: External interrupt request register)
The bit configuration of the interrupt/DTP source register (EIRR) is shown below.
EIRR
Address: 00000D
The interrupt/DTP source register (EIRR) is set to "1" if the edge or level signal set in the
detection condition selection bits (LB, LA) of the request level setting register (ELVR) is input to
the external interrupt pin.
If the register is set to "1", an interrupt request for the corresponding interrupt/DTP channel is
generated when the interrupt/DTP request enable bits (EN) of ENIR are set to "1".
If the register is set to "0", it is cleared.
If the register is set to "1", the interrupt request status is not affected.
Notes:
• Reading by read-modify-write type instructions always read "1". If multiple external interrupt
request outputs are enabled (ENIR: EN7 to EN0=1), only the bits for which the CPU accepts an
interrupt (bits for which "1" was set in EN7 to EN0) are cleared to "0". No other bits must be
cleared unconditionally.
• When corresponding DTP/external interrupt enable bit (ENIR: EN) is set to "1", the value of the
DTP/external interrupt factor bit (EIRR: ER) is valid.
When the DTP/external interrupt has disabled (ENIR: EN=0), the DTP/external interrupt factor bit
might be set regardless of the existence of the DTP/external interrupt factor.
• Please clear DTP/external interrupt factor bit (EIRR: ER) corresponding to immediately before
permitting DTP/external interrupt.
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Request level setting register (ELVR: External level register)
The bit configuration of the request level setting register (ELVR) is shown below.
Address: 00000E
Address: 00000F
The request level setting register (ELVR) is used to select a request detection level. Two bits
are assigned for each pin, as shown in Table 16.2-1. If the setting for a request input indicates a
level, the corresponding level will be set again when it is cleared, provided the input is active.
Table 16.2-1 ELVR assignment (LA0 to LA7, LB0 to LB7)
LBx
bit 15 14 13
ER7 ER6 ER5 ER4 ER3
H
R/W R/W R/W R/W R/W
bit 7 6 5
LB3 LA3 LB2
H
R/W R/W R/W R/W R/W
bit 15 14 13
LB7 LA7 LB6
H
R/W R/W R/W R/W R/W
LAx
0 0
0 1
1 0
1 1
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
12 11 10 9
ER2 ER1 ER0
R/W R/W R/W
4 3 2 1
LA2 LB1 LA1 LB0
R/W R/W R/W
12 11 10 9
LA6 LB5 LA5 LB4
R/W R/W R/W
Request by "L" level
Request by "H" level
Request by rising edge
Request by falling edge
8 Initial value
XXXXXXXX
B
0 Initial value
LA0 00000000
B
8 Initial value
LA4 00000000
B
Operation
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