Up/Down Count Register (Ch.0/Ch.1) (Udcr0/Udcr1) - Fujitsu MB90480 Series Hardware Manual

F2mc-16lx 16-bit microcontroller
Table of Contents

Advertisement

13.3.5 Up/down count register (ch.0/ch.1) (UDCR0/UDCR1)

This section describes the configuration and explains the function of up/down count
register (ch.0/ch.1) (UDCR0/UDCR1).
Up/down count register (ch.0/ch.1) (UDCR0/UDCR1)
The bit configuration of the up/down count register (ch.0/ch.1) (UDCR0/UDCR1) is shown
below.
Figure 13.3-6 Bit configuration of up/down count register (ch.0/ch.1) (UDCR0/UDCR1)
UDCR 1
ch.1 Address: 000069
UDCR 0
ch.0 Address: 000068
This register is an 8-bit count register. With an internal prescaler or AIN/BIN pin input, an up/
down count operation is performed. It operates as a 16-bit count register in the 16-bit count
mode. In this case, the high-order 8-bit setting of the control register is disabled.
Writing to this register directly is not allowed. To write to this register, be sure to write via PCR.
The value to be written to this register must first be written to RCR, and then it is transferred
from RCR value to this register by setting the CCRL: CTUT bit to "1" (reloading by software).
This register requires word access for reading.
bit
15
14
13
D17
D16
D15 D14
H
R
R
R
bit
7
6
5
D07
D06
D05 D04
H
R
R
R
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
12
11
10
9
D13
D12
D11
R
R
R
R
4
3
2
1
D03
D02
D01
R
R
R
R
8
Initial value
D10
00000000
B
R
0
Initial value
D00
00000000
B
R
273

Advertisement

Table of Contents
loading

Table of Contents