CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
12.5.6 Timing of input capture
This section describes a capture timing of the input signal for input capture.
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Capture timing to input signal
Figure 12.5-10 shows the capture timing of input signal for input capture.
Figure 12.5-10 Capture timing of input signal for input capture
φ
N
N+1
Counter value
Input capture
Valid edge
Capture signal
N+1
Capture register
Interrupt
245