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CHAPTER 19 UART
19.5.2 Operation in Synchronous Mode (Operation Mode 2)
The transfer operation becomes clock-synchronous when the UART operates in
operation mode 2 (CLK synchronous mode).
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Operation in CLK synchronous mode (operation mode 2)
❍ Transfer Data Format
In synchronous mode, 8-bit data is transferred with LSB first, and no start bit or no stop bit is
added.
Figure 19.5-5 shows the data format in synchronous mode.
Send and receive clock
Send and receive data
❍ Clock Supply
In a clock synchronous (expanded I/O serial) operation, a number of clock equivalent to the
number of bits in the transmission/reception data must be supplied.
When an internal clock (dedicated baud rate generator or internal timer) is selected, a data
reception synchronous clock will be supplied automatically when data is sent.
If an external clock is selected, the serial output register (SODR) in the UART of the
transmission side system must contain data. After confirmation that TDRE of the SSR is "0",
clock for one byte must be supplied correctly from the outside.
Always set the mark level "H" before and after sending data.
❍ Error Detection
Only overrun errors can be detected. Parity and framing errors cannot be detected.
430
Figure 19.5-5 Transfer data format (in CLK synchronous mode)
Send data write
RXE,TXE
LSB
1
0
1
1
0
Data
Mark level
0
1
0
MSB
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