Watchdog Timer Configuration - Fujitsu MB90480 Series Hardware Manual

F2mc-16lx 16-bit microcontroller

Table of Contents

10.3 Watchdog Timer Configuration

The watchdog timer is composed of the following five blocks:

• Count clock selector

• Watchdog counter (2-bit counter)

• Watchdog reset generation circuit

• Counter clear control circuit

• Watchdog timer control register (WDTC)

Block diagram of watchdog timer

Figure 10.3-1 is a block diagram of the watchdog timer.

Watch mode start

Timebase timer mode start

Sleep mode start

Hold state start

Stop mode start

HCLK frequency

divided by 2

HCLK: Oscillation clock

SCLK: Sub-clock

❍ Count clock selector

This circuit selects the count clock of the watchdog timer from among four types of timebase

timer output and four types of watch timer output. This selection determines the time for

generating a watchdog reset.

❍ Watchdog counter (2-bit counter)

This is a 2-bit up-counter that uses timebase timer output as the count clock.

Figure 10.3-1 Block diagram of watchdog timer

Watchdog timer control register (WDTC)

WRST ERST SRST WTE WT1 WT0

Watchdog timer

Counter clear

control circuit

(Timebase timer counter)

CHAPTER 10 WATCHDOG TIMER

WDCS bit in watch timer control register (WTC)

SCM bit in clock selection register (CKSCR)

To internal reset

generation circuit