Fujitsu MB90480 Series Hardware Manual page 271

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Program example of output compare
Example of setting procedure
2-channel independent output compare operation
(7FFFF, BFFFF), interrupt generation, no compare
clear
<Initial setting>
•
Control free-running timer
Set control register
Clock selection>>
Interrupt request flag>>
Interrupt request enable>>
Count operation>>
Initialization condition of timer>>
TCDT clear>>
Count clock>>
Set timer data value
•
Control output compare
Set control register
Reverse operation of pin
output level>>
Pin output enable>>
Specify pin output level>>
Interrupt request flag>>
Interrupt request enable>>
Set operation enable>>
Set compare value ch.0
Set compare value ch.1
•
Interrupt related
Set interrupt level
Set interrupt level
Set I flag
<Start>
•
Start output compare
Interrupt control
Start compare operation
•
Start free-running timer
Start count operation
Program example
void OUTPUT01_sample(void)
{
}
void freerun_initial(void)
{
IO_TCCS.word = 0x0020; /* Setting value=0000_0000_0010_0000 */
TCCS
.ECKE
.IVF
.IVFE
.STOP
.MODE
.SCLR
.CLK2-0
IO_TCDT = 0x0000;
TCDT
}
void OUTPUT01_initial(void)
{
Register name. bit name
IO_OCS01.word = 0x0C00;/* Setting value=0000_1100_0000_0000 */
OCS01
.CMOD
.OTE1,OTE0
.OTD1,OTD0
.ICP1,ICP0
.ICE1,ICE0
.CST1.CST0
OCCP0
IO_OCCP0 = BFFF;
OCCP1
IO_OCCP1 = 7FFF;
IO_ICR08.byte = 0x00;
ICR08
ICR09
IO_ICR09.byte = 0x00;
(CCR)
__EI();
}
void OUTPUT01_start(void)
{
Register name. bit name
IO_OCS01.word = 0x0C30;/* bit5-4 = 11
OCS01 .ICE1.ICE0
OCS01 .CST1.CST0
IO_OCS01.word = 0x0C33;/* bit1-0 = 11
}
void freerun_start(void)
Register name. bit name
{
TCCS .STOP
IO_TCCS.bit.STOP = 0;
}
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
freerun_initial();
OUTPUT01_initial();
OUTPUT01_start();
freerun_start();
/* bit15 = 0 ECKE internal clock source*/
/* bit7 = 0 IVF interrupt request flag */
/* bit6 = 0 Enable IVFE interrupt */
/* bit5 = 1 Disable STOP count */
/* bit4 = 0 Initialize by MODE reset, clear bit */
/* bit3 = 0 Initialize SCLR free-running timer value */
/* bit2-0 = 000 CLK2-0 count clock φ/4=32MHz/4 */
/* Initialize timer data value */
/* bit15-13 = 000
/* bit12 = 0
/* bit11-10 = 11
/* bit9-8 = 00
/* bit7-6 = 00
/* bit5-4 = 00
/* bit3-2 = 00
/* bit1-0 = 00
/* Set Compare register ch.0 */
/* Set Compare register ch.1 */
/* Set output compare ch.0 interrupt level
(arbitrary value) */
/* Set output compare ch.1 interrupt level
(arbitrary value) */
/* Enable interrupt */
/* bit4 = 0
Undefined bit*/
Reverse CMOD ch.0,ch.1 level */
Enable OTE1,OTE0 pin output */
OTD1,OTD0 compare pin output 0 */
Clear ICP1,ICP0 output compare flag */
Disable
ICE1,ICE0 output compare interrupt */
Undefined bit */
Disable CST1,CST0 compare
operation */
Enable ICE1,ICE0 output compare
interrupt */
Enable CST1,CST0 compare
operation */
Enable STOP count */
(Continued)
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