Fujitsu MB90480 Series Hardware Manual page 101

2
■
Operation of EI OS
ISD
I/OA
BAP
ICS
DCT
(1) The EI
(2) The interruption controller sets the EI
register (ICR) setting.
(3) The address pointers for the transfer origination or destination are read from the EI
descriptor.
(4) The data is transferred based on the address pointers for the transfer origination and
destination.
(5) The interrupt request flag bit of the peripheral function is cleared after the data transferring
completed.
Figure 3.7-1 Operation of EI
Memory Space
by I/OA
CPU
(3)
(3)
by BAP
(4)
2
: EI OS descriptor
: I/O address pointer
: Buffer address pointer
2
: EI OS channel select bit of Interrupt control register (ICR)
: Data counter
2
OS will be activated from the peripheral function (resource).
Peripheral function (Resource)
Resource
register
by ICS
ISD (2)
Buffer
Count by DCT
2
OS descriptor according to the interrupt control
CHAPTER 3 INTERRUPT
2
OS
Resource register
(5)
Interrupt request (1)
Interrupt Control Register (ICR)
Interrupt controller
2
OS
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