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Block diagram of pin related to 8/16-bit PPG timer
Figure 15.2-3 Block diagram of pin related to 8/16-bit PPG timer
Port data register (PDR)
PDR
PDR
Port direction register
DDR
DDR
Standby control : Stop mode (SPL=1), timebase timer mode (SPL=1), watch mode (SPL=1)
Read
Output latch
Write
(DDR)
Direction latch
Write
Read
CHAPTER 15 8/16-BIT PPG TIMER
Peripheral function output
(PPG0 to 5)
Peripheral function output enable
Standby control
P-ch
Pin
N-ch
(SPL=1)
321
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