Fujitsu MB90480 Series Hardware Manual page 587

• Condition 2 in which an interrupt (INT bit = 1) upon detection of " AL bit = 1 " does not occurs
When an instruction which generates a start condition by enabling I
1) is executed (setting the MSS bit in the IBCR register to "1") with the I
by another master.
This is because, as shown in Figure 27.3-2, when the other master on the I
communication with I
no start condition detected (BB bit = 0).
Figure 27.3-2 Diagram of timing at which an interrupt upon detection of " AL bit = 1 " does not occur
Start Condition
SCL pin
SDA pin
EN bit
MSS bit
AL bit
BB bit
INT bit
If a symptom as described above can occur, follow the procedure below for software
processing.
1) Execute the instruction that generates a start condition (set the MSS bit to "1").
2) Use, for example, the timer function to wait for the time * for three - bit data transmission at
2
the I C transfer frequency set in the ICCR register.
Example: Time for three - bit data transmission at an I
3) Check the AL and BB bits in the IBSR register and, if the AL and BB bits are 1 and 0,
respectively, set the EN bit in the ICCR register to 0 to initialize I
bits are not so, perform normal processing.
CHAPTER 27 I
2
C disabled (EN bit = 0), the I
The INT bit interrupt does not
occur in the ninth clock cycle.
SLAVE ADDRESS
3
)} x 3 = 30 μs
{1/(100 x 10
2
C INTERFACE (ONLY MB90485 SERIES)
2
C bus enters the occupied state with
ACK DAT
2
C transfer frequency of 100 kHz
2
C operation (EN bit =
2
C bus occupied
2
C bus starts
Stop Condition
ACK
0
0
2
C. When the AL and BB
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