Fujitsu MB90480 Series Hardware Manual page 606

APPENDIX
Table B-1 I/O Map (4/8)
Address
Output compare register (ch.0)
4A
H
lower
Output compare register (ch.0)
4B
H
upper
Output compare register (ch.1)
4C
H
lower
Output compare register (ch.1)
4D
H
upper
Output compare register (ch.2)
4E
H
lower
Output compare register (ch.2)
4F
H
upper
Output compare register (ch.3)
50
H
lower
Output compare register (ch.3)
51
H
upper
Output compare register (ch.4)
52
H
lower
Output compare register (ch.4)
53
H
upper
Output compare register (ch.5)
54
H
lower
Output compare register (ch.5)
55
H
upper
Output compare control register
56
H
(ch.0,1)
Output compare control register
57
H
(ch.0,1)
Output compare control register
58
H
(ch.2,3)
Output compare control register
59
H
(ch.2,3)
Output compare control register
5A
H
(ch.4,5)
Output compare control register
5B
H
(ch.4,5)
5C Input capture register (ch.0) lower
H
5D Input capture register (ch.0) upper
H
5E Input capture register (ch.1) lower
H
5F Input capture register (ch.1) upper
H
60 Input capture control register
H
61
H
584
Register Abbreviation Access
OCCP0 R/W
OCCP1 R/W
OCCP2 R/W
OCCP3 R/W
OCCP4 R/W
OCCP5 R/W
OCS01 R/W
OCS01 R/W
OCS23 R/W
OCS23 R/W
OCS45 R/W
OCS45 R/W
R
IPCP0
R
R
IPCP1
R
ICS01 R/W
Reserved area
Resource Initial value
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
16-bit output
00000000
timer
output compare
(ch.0 to ch.5)
00000000
00000000
00000000
0000--00
---00000
0000--00
---00000
0000--00
---00000
XXXXXXXX
16-bit output
XXXXXXXX
timer
XXXXXXXX
input capture
XXXXXXXX
(ch.0, ch.1)
00000000
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B