Table of Contents
Advertisement
CHAPTER 9 TIMEBASE TIMER
9.4
Timebase Timer Interrupt
The timebase timer can generate the interrupt request caused by an overflow of the
specified bit in the timebase timer counter (interval timer function).
■
Timebase timer interrupt
When the timebase timer counter counts up using the internal count clock and the bit for the
selected interval timer overflows, the interrupt request flag bit (TBOF) of the timebase timer
control register (TBTC) is set to "1". In this event, if an interrupt request is permitted because
the interrupt request permit bit (TBIE) is set to "1", an interrupt request is generated in the CPU.
Clear this interrupt request by writing "0" to the TBOF bit using the interrupt processing routine.
Incidentally, TBOF bit is set when the specified bit overflows regardless for the value for the
interrupt request permit bit (TBIE).
Note:
Clearing of the interrupt request flag bit (TBOF) in the timebase timer control register (TBTC) must be
implemented in the state where the timebase timer interrupt is prohibited by the interrupt request
permit bit (TBIE) or by the interrupt level mask register (ILM) setting of the processor status (PS).
References:
•
If the TBOF bit is set to "1", an interrupt request is generated immediately when the TBIE
bit is switched from prohibit (0) to permit (1).
μDMAC cannot be used in the timebase timer.
•
Timebase timer interrupt and μDMAC
■
Table 9.4-1 lists timebase timer interrupts and μDMAC.
Table 9.4-1 Timebase timer interrupt and μDMAC
Interrupt level setting register
Interrupt No.
Register name
#41
ICR15
x: Not used
Note:
ICR15 is commonly used by the timebase timer interrupt, the watch timer interrupt, and flash write.
Although interrupt can be used for these three purposes, the interrupt level is the same.
192
Address of the vector table
Address
Low-order
0000BF
FFFF58
H
High-order
Bank
FFFF59
FFFF5A
H
H
μDMAC
x
H
Advertisement
Table of Contents
