Configuration And Functions Of Μpg Timer Registers - Fujitsu MB90480 Series Hardware Manual

F2mc-16lx 16-bit microcontroller
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CHAPTER 26 μPG TIMER (ONLY MB90485 SERIES)
26.2 Configuration and Functions of μPG Timer Registers
This section describes the configuration of the registers used in the μPG timer and
their functions.
μPG control/status register (PGCSR)
The bit configuration of the μPG control/status register (PGCSR) is shown below.
7
00008E
PEN0 PE1
H
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
The functions of the bits in the μPG control/status register (PGCSR) are listed below.
[bit7] PEN0 (operation enable)
This bit is used to enable μPG timer operation.
PEN0
0
1
This bit is initialized at reset.
[bit6, bit5] PE1, PE0 (output enable)
These bits are used to control the pulse output external pin.
PE1
0
0
1
1
These bits are initialized to "00
552
6
5
4
3
PE0 PMT1 PMT0
(0)
(0)
(0)
(0)
Stop (retaining "L" level) (initial value)
PG operation allowed
PE0
0
General-purpose port pin (pulse output prohibited) (initial value)
1
MT00 pulse output pin only (output allowed)
0
MT01 pulse output pin only (output allowed)
1
MT00,MT01 pulse output pin (output allowed)
" at reset.
B
2
1
0
PGCSR
μPG control status register
-
-
-
(-)
(-)
(-)
Read/write
(-)
(-)
(-)
Initial value
Function
Operation control function

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