Fujitsu MB90480 Series Hardware Manual page 608

APPENDIX
Table B-1 I/O Map (6/8)
Address
83
H
*
84 divide ratio control register
H
85
H
*
86 divide ratio control register
H
87
H
*
88 bus status register
H
*
89 bus control register
H
*
8A bus clock select register
H
*
8B bus address register
H
*
8C bus data register
H
8D
H
* μPG control status register
8E
H
8F to
H
9B
H
μDMAC status register
9C
H
μDMAC status register
9D
H
Program address detection control
9E
H
status register
Delay interrupt source generate/
9F
H
delete register
Low-power consumption mode
A0
H
register
A1 Clock select register
H
A2 , A3
H H
μDMAC stop status register
A4
H
Automatic ready function selection
A5
H
register
External address output control
A6
H
register
A7 Bus control signal control register
H
A8 Watchdog timer control register
H
A9 Timebase timer control register
H
AA Watch timer control register
H
AB
H
μDMAC control register
AC
H
μDMAC control register
AD
H
586
Register Abbreviation Access
Reserved area
DIVR1 R/W
Reserved area
DIVR2 R/W
Reserved area
IBSR R
IBCR R/W
ICCR R/W
IADR R/W
IDAR R/W
Reserved area
PGCSR R/W
Use prohibited
DSRL R/W
DSRH R/W
PACSR R/W
DIRR R/W
LPMCR W,R/W
CKSCR R,R/W
Reserved area
DSSR R/W
ARSR W
HACR W
EPCR W
WDTC R,R/W
TBTC W,R/W
WTC R,R/W
Reserved area
DERL R/W
DERH R/W
Resource Initial value
PWC (ch.1)
PWC (ch.2)
00000000
00000000
2
I C --0XXXXX
-XXXXXXX
XXXXXXXX
μPG
00000---
μDMAC
00000000
μDMAC
00000000
Address Match
Detection 00000000
Function
Delay interrupt
generate module
Low-power
consumption 00011000
power
Low-power
consumption 11111100
power
μDMAC
00000000
External pin 0011--00
External pin
External pin 1000*10-
Watchdog timer XXXXX111
Timebase timer 1XX00100
Watch timer 10001000
μDMAC
00000000
μDMAC
00000000
------00
B
------00
B
B
B
B
B
B
B
B
B
B
-------0
B
B
B
B
B
********
B
B
B
B
B
B
B