Table of Contents
Advertisement
[bit5] STOP
This bit sets whether to enable or disable the counting by the free-running timer. If this bit is
set to "1", the timer stops counting, and if it is set to "0", the timer starts counting.
0
1
If the free-running timer stops counting, the output compare operation also stops.
[bit4] MODE
This bit specifies the initialization conditions of the free-running timer.
If set to "0", the reset and clear bit (bit3: SCLR) initialize the counter value.
If set to "1", in addition to the reset and clear bit (bit3: SCLR), matching the compare clear
register (CPCLR) value with the free-running timer, initializes the counter value.
0
1
The counter value initialization occurs at the point where the counter value changes.
[bit3] SCLR
This bit initializes the value of the free-running timer to "0000".
Writing "1" initializes the counter value to "0000". Writing "0" has no effect. The read value is
always "0". The counter value initialization occurs synchronizing with the counter value
change point.
0
1
If it is initialized at the time of stopping the timer, write "0000" to the data register.
Note:
After "1" is written, the counter value of this bit is not initialized to the following count clock when "0"
is written.
Count permit (operation) (initial value)
Count prohibit (stop)
Initialized by reset and clear bit (initial value)
Initialized by reset, clear bit, and compare clear register
No effect (initial value)
Initializes the counter value to "0000"
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
227
Advertisement
Table of Contents
