Fujitsu MB90480 Series Hardware Manual page 680

Multiple
Example of multiple interrupt
Multiple interrupt operations
Multiplex
.................................................. 175
Multiplex mode
Pin states in external bus 16-bit data bus mode and multiplex
16-bit external bus mode
Pin states in external bus 8-bit data bus mode and multiplex
8-bit external bus mode
N
NCC
Flag change suppress prefix (NCC)
Non-multiplex
............................................ 175
Non-multiplex mode
Pin states in external bus 16-bit data bus mode and non-
multiplex 16-bit external bus mode
Pin states in external bus 8-bit data bus mode and non-
multiplex 8-bit external bus mode
O
OCCP
Output compare register (OCCP0 to 5)
OCS
Output compare control register (OCS01/23/45)
ODR
Port output pin registers (ODR7,ODR4)
On-board
Pins used for Fujitsu standard serial on-board
................................................ 507
writing
One-Shot
One-Shot measurement and repeated
......................................... 540
measurement
One-shot
One-shot operation mode
Operation in internal clock mode
(One-Shot Mode)
Operating
Setting and Operating State
Operation
.................................................. 333
Operation mode
................................. 154, 368, 423
Operation modes
Selection of operation mode
Operation state
Confirmation of operation state
Oscillation
Oscillation clock frequency and serial clock input
............................................. 508
frequency
Reset state waiting for stable oscillation
Oscillation stabilization
Oscillation stabilization wait time
Reset factors and oscillation stabilization wait
...................................................... 98
time
Sub-clock oscillation stabilization wait time
............................................... 215
function
Timer function for Oscillation Stabilization
............................................ 193
Wait Time
658
.................................. 61
................................... 61
.......................... 144
........................... 145
........................... 41
............ 146
.............. 147
..................... 230
......... 230
................... 183
...................................... 537
................................... 308
................................... 468
.................................. 533
.............................. 536
..................... 99
................... 121, 149
Oscillator
Connection of oscillator and external clock
Other
............................................ 575
Other considerations
.......................................................... 503
the others
Outline
........................................... 454
Outline of operations
Output compare
Block diagram of output compare
List of output compare registers
Output compare control register (OCS01/23/45)
Output compare register (OCCP0 to 5)
Program example of output compare
Overview
.......................................................... 503
Overview
P
Package
Package dimensions (LQFP-100)
Package dimensions (QFP-100)
Package of corresponding products
PACSR
Program Address Detection Control Status Register
............................................. 461
(PACSR)
PADR
Functions of Program Address Detection Registers
(PADR0 and PADR1)
Program Address Detection Registers
(PADR0,PADR1)
Patch
Flow of Patch Processing
Operation of Address Match Detection Function at Storing
Patch Program in E
PC
............................................ 36
Program counter (PC)
PCB
Bank select prefix (PCB,DTB,ADB,SPB)
Program counter bank register (PCB)<Initial value: value in
........................................... 37
reset vector>
PDR
Port registers (PDR0 to PDRA)
Peripheral devices
Conditions for external connection of peripheral
................................................ 350
devices
PGCSR
μPG control/status register (PGCSR)
Pin
Pin related to μPG timer
....................................... 550
Pin assignment
Pin assignment diagram (LQFP-100)
Pin assignment diagram (QFP-100)
Pin functions
....................................................... 11
Pin functions
Pin state
Pin state in single chip mode
Pin states after mode data Is read
............... 122
........................... 220
............................. 229
........ 230
.................... 230
....................... 249
............................... 7
................................. 8
............................. 5
............................. 464
.................................. 463
..................................... 470
2
...................... 469
PROM
.................. 40
.............................. 180
...................... 552
......................... 10
............................. 9
................................. 143
............................ 105