Fujitsu MB90480 Series Hardware Manual page 133

❍ System clock generator circuit
This circuit generates an oscillation clock (HCLK) by using an oscillator connected to the high-
speed oscillation pin. Also, an external clock can be input to it.
❍ Sub-clock generator circuit
This circuit generates a sub-clock (SCLK) by using an oscillator connected to the low-speed
oscillation pin. Also, an external clock can be input to it.
❍ PLL multiplier circuit
This circuit multiplies an oscillation clock by using PLL oscillation and supplies it to the CPU
clock selector.
❍ Clock selector
This circuit selects clocks from among the main clock, sub-clock, and four PLL clocks supplied
to the CPU clock control circuit and peripheral clock control circuit.
❍ Clock selection register (CKSCR)
This register changes between the oscillation clock and PLL clocks, selects the oscillation
stabilization wait time, and selects the multiplication rate of the PLL clocks.
❍ PLL output selection register (PLLOS)
Use this register to specify doubling of the multiply-by rate specified in the CKSCR register for
the PLL to be used when a machine clock is used at a frequency of 20 to 25 MHz.
❍ Selector for the oscillation stabilization wait time
This circuit selects the oscillation stabilization wait time of the oscillation clock when the stop
mode is reset and during watchdog reset. Four types of the timebase timer output are selected.
CHAPTER 5 CLOCKS
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