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19.2
Configuration of UART
The UART consists of the serial mode register, serial control register, serial status
register, communication prescaler control register and serial input/output register.
■
UART Block Diagram
Figure 19.2-1 shows a block diagram of the UART.
Control signal
Dedicated baud
rate generator
PPG1
(internal connection)
External clock
SIN0
Reception state
detection circuit
Serial
mode
register
(SMR)
Figure 19.2-1 Block diagram of the UART
Clock
selector
Reception
circuit
clock
Reception control
circuit
Start-bit
detector
circuit
Reception
bit counter
Reception
parity
counter
Reception
shift register
Reception
DMAC reception
control circuit
error transmission
Serial input
signal (to CPU)
register (SIDR)
2
F
MC-16LX bus
MD1
PEN
MD0
P
Serial
CS2
SBL
control
CS1
CL
register
CS0
A/D
(SCR)
REC
SCKE
REX
SOE
TXE
Reception interrupt (to CPU)
SCK0
Transmission clock
Send interrupt (to CPU)
Transmission
control circuit
Transmission
start circuit
Transmission
bit counter
Transmission
parity counter
SOT0
Transmission
shift register
Transmission
start
Serial output
register (SODR)
PE
ORE
Serial
FRE
status
RDRF
register
TDRE
(SSR)
BDS
RIE
TIE
Control signal
CHAPTER 19 UART
409
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