Method For Starting The Flash Memory's Automatic Algorithm - Fujitsu MB90480 Series Hardware Manual

F2mc-16lx 16-bit microcontroller
Table of Contents

Advertisement

CHAPTER 23 2M/3M BIT FLASH MEMORY
23.4 Method for Starting the Flash Memory's Automatic
Algorithm
There are four kinds of commands for starting the automatic algorithm for flash
memory: read/reset, write, chip erase, and sector erase. For sector erase operations,
control of suspension and resuming is provided.
Command sequence table
Table 23.4-1 lists the commands used for flash memory write/erase operations. Although the
data for writing to the command register is indicated in units of bytes, use word access during
actual operations. The contents of the upper byte are ignored in this case.
Table 23.4-1 Command sequence table
1st bus write
Bus
Command
write
sequence
cycle
Address
Read/reset*
1
FxXXXX
Read/reset*
4
FxAAAA XXAA
Write program
4
FxAAAA XXAA
Chip erase
6
FxAAAA XXAA
Sector erase
6
FxAAAA XXAA
Sector erase suspend
Sector erase resume
RA: Read address
PA: Write address. Only even addresses can be specified.
SA: Sector address (Refer to Section "
RD: Read data
PD: Write data; only words can be specified
* : Both read and reset commands allow the flash memory to be reset to read mode.
Notes:
• The address Fx in the table represents FF, FE, FD or FC. Specify the actual value corresponding
to the bank to be accessed in each operation.
• The address in the table indicates the value in the CPU memory map. Addresses and data are
indicated in hexadecimal representation; "X" indicates an arbitrary value.
486
2nd bus write
cycle
cycle
Data
Address
Data
XXF0
-
-
Fx5554
XX55
Fx5554
XX55
Fx5554
XX55
Fx5554
XX55
Entering data (xxB0H) at address "FxXXXX" will suspend a erasure in sector erase mode.
Entering data (xx30H) at address "FxXXXX" will resume erasure in sector erase suspend mode.
23.2 Sector Configuration of 2M/3M Bit Flash Memory
3rd bus write
4th bus write
cycle
cycle
Address
Data
Address
Data
-
-
-
FxAAAA
XXF0
RA
PA
FxAAAA XXA0
(even)
(word)
FxAAAA
XX80
FxAAAA
XXAA
FxAAAA
XX80
FxAAAA
XXAA
")
5th bus write
6th bus write
cycle
Address
Data
Address
-
-
-
-
RD
-
-
-
PD
-
-
-
Fx5554
XX55
FxAAAA
SA
Fx5554
XX55
(even)
cycle
Data
-
-
-
XX10
XX30

Advertisement

Table of Contents
loading

Table of Contents