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1
1.3.5 Floating-point Status Register: FPSR (CR7)
b0
1
2
FS
FX
FU
0
0
0
b16
17
18
EX
EU
0
0
0
b
Bit Name
0
FS
Floating-point Exception
Summary Bit
1
FX
Inexact Exception Flag
2
FU
Underflow Exception Flag
3
FZ
Zero Divide Exception Flag
4
FO
Overflow Exception Flag
5
FV
Invalid Operation Exception
Flag
6–16
No function assigned. Fix to "0".
17
EX
Inexact Exception Enable
Bit
18
EU
Underflow Exception Enable
Bit
19
EZ
Zero Divide Exception
Enable Bit
20
EO
Overflow Exception
Enable Bit
3
4
5
6
7
FZ
FO
FV
0
0
0
0
0
19
20
21
22
23
EZ
EO
EV
DN
0
0
0
0
Function
Reflects the logical sum of FU, FZ, FO and FV.
Set to "1" when an inexact exception occurs
(if EIT processing is unexecuted (Note 1)).
Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Set to "1" when an underflow exception occurs
(if EIT processing is unexecuted (Note 1)).
Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Set to "1" when a zero divide exception occurs
(if EIT processing is unexecuted (Note 1)).
Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Set to "1" when an overflow exception occurs
(if EIT processing is unexecuted (Note 1)).
Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Set to "1" when an invalid operation exception
occurs (if EIT processing is unexecuted (Note 1)).
Once set, the flag retains the value "1" until
it is cleared to "0" in software.
0: Mask EIT processing to be executed when an
inexact exception occurs
1: Execute EIT processing when an inexact
exception occurs
0: Mask EIT processing to be executed when an
underflow exception occurs
1: Execute EIT processing when an underflow
exception occurs
0: Mask EIT processing to be executed when a
zero divide exception occurs
1: Execute EIT processing when a zero divide
exception occurs
0: Mask EIT processing to be executed when an
overflow exception occurs
1: Execute EIT processing when an overflow
exception occurs
CPU PROGRAMMING MODEL
8
9
10
11
0
0
0
0
24
25
26
27
CE
CX
CU
CZ
1
0
0
0
0
1-6
M32R-FPU Software Manual (Rev.1.01)
1.3 Control Registers
12
13
14
b15
0
0
0
0
28
29
30
b31
CO
CV
RM
0
0
0
0
<At reset release: H0000 0100>
R
R
R
R
R
R
R
0
R
R
R
R
W
–
W
W
W
W
W
0
W
W
W
W
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