Operation Timing In Memory Expansion And Microprocessor Modes; Separate Bus, No-Wait - Renesas Emulation Pod M3062NT3-RPD-E User Manual

5.2 Operation Timing in Memory Expansion and Microprocessor Modes

(1) Separate Bus, No-Wait

Table 5.2 and Figure 5.1 show the bus timing in memory expansion and microprocessor modes (no-
wait).
Table 5.2 Memory expansion and microprocessor modes (no-wait)
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
*1 Calculated by the following formula according to the frequency of BCLK.
td(DB-WR)=
Symbol
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
9
10
-50 [ns]
f(BCLK)x2
Item
( 61 / 84 )
Actual MCU This product
[ns] [ns]
Min. Max. Min.
50
See left
4
See left
0
See left
0 -4
50
See left
4
See left
40
See left
-4
See left
40
See left
0
See left
40
See left
0
See left
50
See left
4
See left
(*1)
See left
0
See left
Max.